A device under test (also designated briefly as “OUT”), for example an integrated circuit, is tested in order to ensure a correct operability of the device. Usually, a DUT is tested with an automatic test equipment (ATE). Test patterns or test stimuli are applied to the OUT by the ATE, which is in the following also briefly named “tester”, and electrical output signals from the OUT are compared to expected data. With this method, different OUT parameters can be proven or characterized, and if necessary the electronic devices (OUT) are split into one or more different categories, for example pass or fail categories or performance categories. In the production test, the influence of different parameters on a proper operation of the DUT can be checked, or proven. Such parameters may be, among others, temperature, humidity, over-voltage or for example, tight timing parameters.
The output timings of digital signals sent from a DUT to the tester can be very tight. The digital signals sent from a DUT to the tester may be coupled to (or synchronized with) a central master clock from the tester, or may be source-synchronous signals. For source-synchronous signals, the bus dock can be generated and provided by the DUT.
If a DUT output arrival time (for example a time at which a data signal from a DUT arrives at an input of a tester, for example referenced to a master clock of the tester) is not known exactly, or if the DUT output arrival time is not stable during a test, the ATE does not know exactly where to place a strobe time (or strobe point-in-time) in order to sample the received data from the DUT, for example to compare the received data from the DUT with expected data.
For example, the capture of data from a source-synchronous bus with clock or data strobe signal can be difficult, when clock and/or strobe (or clock/strobe) and data are separated by long propagation delays (or propagation delay differences), e.g. handled by different chips or hoards, for example in an automated test equipment (ATE). In other words, in some cases it is a challenge to strobe the data in a correct manner in such an environment.
A data strobe channel may for example comprise a (programmable) routing in order to adjust a propagation delay (or a propagation delay difference) between a strobe signal and a data signal. However, this programmable routing of the data strobe channel (which may process the data strobe signal) may sometimes lead to delays that are too long to still capture the data safely.
A tester may comprise a strobe signal channel and a plurality of data signal channels. In a conventional way, the data paths for the plurality of data signals may comprise buffer delays in order to compensate a propagation delay of the strobe signal routing. The required delay matching between the strobe signal and the plurality of data signals can be very difficult, in particular across multiple chips, for example across multiple chips on a channel board for a test system, or across multiple chips connected to so-called DUT-board or load board.
For example, in order to reduce the production test time, a plurality of DUTs on a respectively configured load board can be tested in parallel. The propagation delay (or propagation delay differences) between the different strobe and data signals can be compensated, at least partially, by the above-mentioned buffer delays.
In the US patent application US 2004/0022196 A1, another conventional method for compensating delays, for recovering a bitstream from a signal, is described. Said patent application describes an oversampling bit stream recovery, which is applicable to embedded clocks, where data and clock are embedded on one physical signal.
In view of the above, there is a need for a reliable concept for extracting data from a sequence of data in response to a clock or strobe signal.